Devices having a memory for storing data often employ a memory controller which controls the transfer of write data to the memory and read data from the memory. A central processing unit having one or more processing cores typically provides to the memory controller a system address which defines the memory location at which the write data is to be stored or from which the read data is to be retrieved.
To facilitate data transfers to or from memory, the device may have multiple memory controllers, each of which controls data transfers to and from an assigned portion of the memory. Each memory controller referred to also as a memory controller target way, frequently has a unique logical identification (ID) often referred to as a target logical ID, which uniquely identifies the particular memory controller or memory controller target way. A system address typically includes one or more bits, depending upon the number of memory controllers or memory controller target ways in the device, associated with the target logical ID of the memory controller to which the data transfer is being addressed.
Data being transferred to or from a memory having multiple memory controllers is frequently interleaved so that a first portion of the data passes through one memory controller, a second portion of the data passes through the next memory controller and so on until the last memory controller is reached and then repeats beginning again with the first memory controller. In this manner, the memory controllers can operate in parallel to a degree to increase the speed of the overall data transfer. The size of the data portion handled by each memory controller and being interleaved with the data portions of the other memory controllers, is often described in terms of “target granularity” in which the greater the size of each memory controller portion of the interleaved data, the greater the size of the “grain” of the target granularity.
To further facilitate data transfers to or from memory, each memory controller may have multiple parallel data paths often referred to as channels to the memory portion assigned to that memory controller. Each channel of a memory controller frequently has a logical identification (ID) often referred to as a channel logical ID, which identifies the particular channel of the memory controller. A system address typically includes one or more bits, depending upon the number of channels for each memory controller in the device, associated with the channel logical ID of the channel to which the data transfer is being addressed.
Data being transferred to or from a memory controller having multiple channels is also frequently interleaved so that a first portion of the data passes over one channel of the memory controller, a second portion of the data passes over the next channel of the memory controller and so on until the last channel of the memory controller is reached and then repeats beginning again with the first channel of the memory controller. In this manner, the channels of the memory controller can operate in parallel to a degree to increase the speed of the overall data transfer through the memory controller. The size of the data portion handled by each channel and interleaved with the data portions of the other channels of the memory controller, is often described in terms of channel granularity in which the greater the size of each channel portion of the channel interleaved data, the greater the size of the “grain” of the channel granularity.
In a device having multiple memory controllers and multiple data transfer channels for each memory controller, the memory controllers translate a received system address to a channel address. In some circumstances, it may be useful to reconstruct the original system address from which the channel address was translated. For example, should an error occur in connection with the data transfer associated with a particular channel address, it may be useful to identify the system address corresponding to the channel address at which the error occurred.
However, a channel address frequently has fewer bits than the system address since any one channel typically addresses a smaller portion of the memory than the overall system. In performing the system to channel address conversion, bits of the system address are often discarded by the memory controllers due to interleaving of data transfers among the memory controllers of the device and the interleaving of data transfers among the channels of the memory controllers. As a result, attempts to reconstruct the original system address from a channel address having fewer bits than the original system address, has typically been unreliable, limited to special cases or not readily adapted to a logic implementation in a device.